Ultra low latency · Physical design

You turn a custom chip's design into a physical layout ready to be made, for a trading firm whose systems must answer the market in the least possible time. The seat is in the Ultra Low Latency team at Jane Street in London. Latency is the delay between a signal arriving and the response leaving, and in electronic trading the fastest firm often wins the trade.

An ASIC, an application-specific integrated circuit, is a chip built for a single purpose that cannot be changed once made. Physical design turns the logic, written in RTL, the code that describes what the chip does, into a layout of real circuits on silicon. It decides where each block sits, routes the wires between them and checks that signals arrive in time and power stays within bounds.

This is not a pure physical design seat. The team is small and everyone works across the chip design process, so you lead with physical design but also read and write RTL and weigh decisions that cross between the logic and the layout.